Microprocessor manufacturers are constantly faced with the conflicting requirements of greater processor speed and lower power consumption (i.e., lower heat output). With the packing density of silicon increasing toward tens of millions of transistors per die, microprocessors have become vast metropolises of functions, where many operations can be performed concurrently. Although this has resulted in an increase in processor speeds, the increased complexity and size have made accurate thermal analysis increasingly difficult to achieve.
In a simple integrated circuit, power consumption is typically a function of a switching ratio multiplied by the number of gates, at a known voltage and frequency. However, due to the increased design complexity and concurrent functionality of a microprocessor, the switching ratio is more a function of the actual code patterns being run. Further, since the operational environment determines the cooling rate from the package and external thermal protection, these factors must also be considered. One can attempt to build software models of the transistors, the thermal environment, and a subset of possible code patterns. This, however, is a difficult task to complete for numerous reasons, including the fact that code patterns can only be a small subset of the actual code patterns being run.
One alternative is to analyze the thermal characteristics of the device by testing it while it is still at the wafer level. This has been done using infrared scopes, or by placing temperature sensitive liquids directly on the wafer. Both of these techniques have drawbacks which reduce the accuracy of the analysis. For example, these techniques are at the wafer level, and do not accurately model how the packaged hardware is going to perform, the level of accuracy for area resolution is low, and the number of code patterns that can be applied is limited to tester throughput.